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LHF32KZR
18
4.6 Block Erase Command
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by an block erase
confirm. This command sequence requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status
register data when read (see Figure 5). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit SR.7.
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
erase setup is first written, followed by a bank erase
confirm. After a confirm command is written, device
erases the all unlocked blocks from block 0 to Block
31 block by block. This command sequence requires
appropriate sequencing. Block preconditioning, erase
and verify are handled internally by the WSM
(invisible to the system). After the two-cycle bank
erase sequence is written, the device automatically
outputs status register data when read (see Figure
6). The CPU can detect bank erase completion by
analyzing the output data of the STS pin or status
register bit SR.7.
When the bank erase is complete, status register bit
SR.5 should be checked. If erase error is detected,
the status register should be cleared before system
software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued. If error is detected on a block
during bank erase operation, WSM stops erasing.
Reading the block valid status by issuing Read ID
Codes command or Query command informs which
blocks failed to its erase.
This two-step command sequence of set-up followed
can only occur when V CC =V CC1/2/3/4
can only occur when V CC =V CC1/2/3/4
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to "1". Also, reliable block erasure
and
V PP =V PPH1/2/3 . In the absence of this high voltage,
block contents are protected against erasure. If block
erase is attempted while V PP ≤ V PPLK , SR.3 and SR.5
will be set to "1". Successful block erase requires that
the corresponding block lock-bit be cleared or if set,
that WP#=V IH . If block erase is attempted when the
corresponding block lock-bit is set and WP#=V IL ,
SR.1 and SR.5 will be set to "1".
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Bank Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to "1". Also, reliable bank erasure
and
V PP =V PPH1/2/3 . In the absence of this high voltage,
block contents are protected against erasure. If bank
erase is attempted while V PP ≤ V PPLK , SR.3 and SR.5
will be set to "1". When WP#=V IH , all blocks are
erased independent of block lock-bits status. When
WP#=V IL , only unlocked blocks are erased. In this
case, SR.1 and SR.5 will not be set to ‘‘1‘‘. Bank
erase can not be suspended.
4.7 Bank Erase Command
This command followed by a confirm command
(D0H) erases all of the unlocked blocks. A bank
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